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Description: VHDL Library for 8254 timer/counter core
Platform: |
Size: 627712 |
Author: Alireza |
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Description: IC内核的设计源码！其中包含MP3内核，CPU内核，I2C内核等多达式种IC设计的源码！-IC design of the kernel source code! MP3 contains one of the kernel, CPU core, I2C kernel up-type species such as IC design source!
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Size: 27160576 |
Author: hehuilong |
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Description: a jpeg compression core
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Size: 317440 |
Author: sandeep |
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Description: This is version 1.5 of the MC8051 IP core.
Platform: |
Size: 421888 |
Author: Bill Guan |
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Description: 调用FPGA的IP核实现FFT运算，在xilinx的vertex4sx55FPGA的实现-Call FPGA implementation of the IP core FFT computation, in the Xilinx implementation of the vertex4sx55FPGA
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Size: 1287168 |
Author: 徐成发 |
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Description: 本文研究了SMBus
规范，介绍了典型的基于片上系统（SoC）设计的知识产权核（IP）实现，采用自顶向下
(Top-down)的集成电路设计方法完成了设计，并架构了基于总线功能模型(BFM)的验证平台
完成功能仿真，顺利完成了逻辑综合和时序仿真。FPGA 验证和投片后测试均表明设计具有
良好的性能。-This paper studies the SMBus specification, based on the introduction of the typical system-on-chip (SoC) intellectual property core design (IP) implementation, using top-down (Top-down) of the integrated circuit design methods achieve a design and architecture based on the total Line functional model (BFM) achieve functional verification platform for simulation, successfully completed a logic synthesis and timing simulation. FPGA silicon validation and post-tests show that the design has good performance.
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Size: 256000 |
Author: caorui |
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Description: cic抽取滤波器ip核，用于射频采样数字下变频模块的核心数字信号处理部分.此ip核已经过ise10.2验证-CIC decimation by 4 filter，used in Direct RF sampling of GPS signal. the core dsp block in a frondend design
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Size: 31744 |
Author: mimidabuda |
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Description: vhdl 写的 PCI IP核程序，已经过测试-pci ip core
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Size: 23552 |
Author: planet1997 |
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Description: arm 7 core manual is good reference.
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Size: 41984 |
Author: li |
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Description: 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。-This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
Platform: |
Size: 61440 |
Author: 普林斯 |
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Description: Project 2D DCT core - specifications and codes-Project 2D DCT core- specifications and codes
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Size: 264192 |
Author: student |
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Description: Project 2D DCT core - specifications and codes-Project 2D DCT core- specifications and codes
Platform: |
Size: 78848 |
Author: student |
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Description: Project 2D DCT core - specifications and codes-Project 2D DCT core- specifications and codes
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Size: 494592 |
Author: student |
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Description: Project 2D DCT core - specifications and codes-Project 2D DCT core- specifications and codes
Platform: |
Size: 10240 |
Author: student |
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Description: 用于模仿密码锁的工作过程。完成密码锁的核心控制功能。可实现数码输入、清除、退位、设置密码、错误提示、系统报警、解除报警、系统关闭等功能。-Used to imitate the work of the code lock process. Locks achieve the core control functions. Digital input can be achieved, clear, step down, set a password, error message, the system alarm, lift the alarm, turn off the functions of the system.
Platform: |
Size: 13312 |
Author: 胡婕 |
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Description: IIC通信协议IP核，描述IIC协议在FPGA上的实现-IIC communications protocol IP core
Platform: |
Size: 448512 |
Author: shigengxin |
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Description: 以FPGA芯片为核心，扩展必要的外围电路，制作一个16*16LED点阵的汉字显示屏，使之能显示16*16LED点阵的汉字4个，如“一”，“二”，“三”，“四”等。要求显示的汉字无闪烁。每个汉字停留时间1秒。-To FPGA chip as the core, the expansion of the necessary external circuit, producing a lattice of 16* 16LED display of Chinese characters so that it can display 16* 16LED lattice four Chinese characters, such as " 1" , " two" , " three" , " four" and so on. Request to display Chinese characters without blinking. Residence time of each character one second.
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Size: 263168 |
Author: 庄青青 |
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Description: USBHostSlave is a USB 1.1 host and Device IP core.
– Supports full speed (12Mbps) and low speed (1.5Mbps) operation.
– USB Device has four endpoints, each with their own independent FIFO.
– Supports the four types of USB data transfer control, bulk, interrupt, and isochronous
transfers.
– Host can automatically generate SOF packets.
– 8-bit Wishbone slave bus interface.
– FIFO depth configurable via paramters.-USBHostSlave is a USB 1.1 host and Device IP core.
– Supports full speed (12Mbps) and low speed (1.5Mbps) operation.
– USB Device has four endpoints, each with their own independent FIFO.
– Supports the four types of USB data transfer control, bulk, interrupt, and isochronous
transfers.
– Host can automatically generate SOF packets.
– 8-bit Wishbone slave bus interface.
– FIFO depth configurable via paramters.
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Size: 6144 |
Author: polito |
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Description: Sensing and planning are at the core of robot motion. Traditionally,
mobile robots have been used for performing various tasks
with a general-purpose processor on-board. This book grew out of
our research enquiry into alternate architectures for sensor-based
robot motion. It describes our research starting early 2002 with the
objectives of obtaining a time, space and energy-efficient solution
for processing sensor data for various robotic tasks.
New algorithms and architectures have been developed for
exploration and other aspects of robot motion. The research has
also resulted in design and fabrication of an FPGA-based mobile
robot equipped with ultrasonic sensors. Numerous experiments
with the FPGA-based mobile robot have also been performed and
they confirm the efficacy of the alternate architecture.
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Size: 1348608 |
Author: moatasem momtaz |
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Description: 基于FPGA的CPU核及其虚拟平台的设计与实现-FPGA-based CPU core and its virtual platform design and implementation of
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Size: 6060032 |
Author: steven |
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